Method of making a transistor structure



J y 1964 w. SHOCKLEY ETAL 3,140,206

METHOD OF MAKING A TRANSISTOR STRUCTURE Original Filed April 11, 1957Z-Sheets-Sheet 1 mll r Hm:

WILLIAM SHOCKLEY ROBERT N. NOYCE INVENTORS BY jMw/m ATTORNEY y 7, 1964w. SHOCKLEY ETAL 3,140,206

METHOD OF MAKING A TRANSISTOR STRUCTURE Original Filed April 11, 19572-Sheets-Sheet 2 I. p. 'n

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Nd-NG WILLIAM SHOCKLEY ROBERT N. NOYCE INVENTOR $44 4mEY United StatesPatent 3,140,206 METHOD OF MAKING A TRANSISTGR STRUCTURE WilliamShockley and Robert N. Noyce, Los Altos, Caiitl, assignors, by directand mesne assignments, to Cievite Corporation, Cleveland, Ohio, acorporation of Uhio Original application Apr. 11, 1957, Ser. No.652,117,

now Patent No. 2,967,985, dated Jan. 10, 1%1. Divided and thisapplication July 1, 1960, Ser. No. 40,342

3 Claims. (Cl. 148186) This invention relates generally to an improvedmethod of making a transistor structure, and more particularly to amethod of making a unipolar field effect transistor structure.

In order to achieve high frequency response, it is neces sary that thechannel in the transistor be short and thin, that is, that it be smallin two direction. To achieve frequency responses in the order ofmegacycles, the length of the channel should be in the order of a fewthousandths of an inch. In constructing a device having a channel withsuch small dimensions, difliculty may be experienced in making amechanically strong structure.

It is an object of the present invention to provide a method offabricating an improved transistor structure suitable for high frequencyoperation.

In copending application Serial No. 652,117, filed April 11, 1957, ofwhich this application is a division, there is described and claimed aunipolar or field effect transistor structure. The structure describedin one embodiment has a relatively thin short channel. The source anddrain regions form a low capacity junction with relatively highbreakdown voltage with the gate and the junction between the channel andgate is abrupt. In accordance with another feature of said invention,the capacitance between the gate regions and the source and draincontacts is minimized.

It is a general object of the present invention to provide improvedmethods for fabricating a unipolar transistor.

It is another object of the present invention to provide a method forforming a unipolar field eifect transistor in which the channel is smallin two directions.

It is another object of the present invention to provide a method offorming a transistor structure in which the source and drain areas forma low capacity junction with relatively high breakdown voltage with thegate and in which the junction between the channel and gate is abrupt.

It is another object of the present invention to provide a method offorming a unipolar field effect transistor in which the capacitance fromgate to the region where contact is made to the source and drain isrelatively small whereby the transistor may be operated at highfrequencies without capacitive loading.

The invention possesses other objects and features of advantage, some ofwhich with the foregoing will be set forth in the following descriptionof the invention. It is to be understood, of course, that the inventionis not to be limited to the disclosure of a particular species of theinvention, as other embodiments thereof may be adopted within the scopeof the appended claims.

Referring to the drawing:

FIGURE 1 is a perspective view of a transistor of the type claimed inthe copending application;

3,140,206 Patented July 7, 1964 FIGURES 2A-C are sectional viewsillustrating the steps for forming a transistor embodying the invention;

FIGURE 3 shows concentration profiles along the lines A-A and BB ofFIGURE 2C;

FIGURES 4A-C show the steps for forming another transistor embodying theinvention;

FIGURE 5 shows concentration profiles along the lines C-C and DD ofFIGURE 4C;

FIGURES 6A-C, FIGURES 7A-B and FIGURES 8A-B show other methods forforming transistors embodying the invention; and

FiGURE 9 shows concentration profiles along the lines E-E and FF ofFIGURE 88.

Referring to FIGURE 1, a transistor structure which may be constructedaccording to the methods of the present invention is illustrated. Thestructure comprises a gate region g which includes a relatively massiveblock of semiconductive material of one conductivity type, for example,p type. A layer of semiconductive material 12 of opposite conductivitytype forms a p-n junction with the block. The layer may be formed bysuitable means, for example, by diffusion. On the other hand, a completeassembly may be formed by the rate growing process with suitablemachining operations being carried out to form a block having a layer ofmaterial of opposite conductivity type forming a p-n junction therewith.The layer of material 12 includes relatively thick regions which formthe source electrode s, and the drain electrode d, and a thin shortintermediate region 0 which forms the channel through which the carriersflow in their travel from source to drain. Suitable ohmic connectionsare made to the base, source and drain.

As is well known, a field effect transistor is operated by increasingand decreasing the width of the space charge region in the channel. Asthe thickness of the space charge region increases, current flow fromsource to drain through the channel decreases. A value is finallyreached where no current flows from source to drain; this is commonlyreferred to as the pinch-off value.

Batteries of appropriate polarity are schematically illustratedconnected between source and drain and across the p-n junction formedbetween the layer 12 and gate g. The signal to be amplified isrepresented by the voltage generator e connected in series with the gatevoltage supply. The voltage modulates the space charge region to controlthe current flow from source to drain.

It is, of course, apparent that although an n-type channel isillustrated forming a junction with a p-type gate that a suitableunipolar field effect transistor may be constructed in which the channelis p-type and the gate block n-type.

Referring to FIGURE 2, a method for forming a channel which is small intwo directions is illustrated. Starting, for example, with a relativelymassive p-type block 13, a relatively thin layer 14 is formed on onesurface thereof. The n-type layer may be formed by exposing the p-typeblock 13 to a source of donors, such that an n-type layer is produced onthe surface. Preferably, the n-type layer is thicker than the finalchannel, dimension a, FIGURE 1, as will presently become apparent. Thelayer of opposite type formed on all surfaces but one is removed. Agroove 16 is then etched, cut, sawed or otherwise formed which extendsthrough the n-type layer into the p-type block 13 to produce a structureof the type illustrated in FIGURE 2B. A second diffusion is carried outin the presence of a source of donors. A relatively thin channel 17 isformed which is connected at its ends to the relatively thick source anddrain 18 and 19, FIG- URE 2C. Ohmic contacts (not illustrated) are thenmade to the block 13, which forms the gate, and to the source and drainregions 18 and 19.

It is noted that the layer in the region of the source and draincontacts is relatively thick. This makes it possible to pinch-off thetransistor at a lower voltage than that at which the space charge regionwidens enough to reach the ohmic source and drain contacts. If the spacecharge region should reach the source and drain contacts, the gateimpedance would be considerably reduced. Another method of decreasingthe likelihood of the space charge region extending to the source anddrain contacts is to heavily dope the region adjacent the contacts. Amethod for producing such a region will be presently described.

The field effect transistor structure described is relatively small. Asa consequence, extra capacitances exist from the gate to the regionswhere contact is made to the source and drain. These capacitances serveto reduce the high frequency characteristics of the device. To improvethese high frequency characteristics, these capacitances should bereduced as much as possible. By making the contact areas to the sourceand drain regions as small as possible, the capacitance between gate andthese contacts is reduced. The capacitance may be reduced further bylowering the concentration gradient at the p-n junction between the gateand source, and the gate and drain. Referring to the structure shown inFIGURE 2, the surface concentrations may be controlled in the diffusionprocess to produce concentration profiles of the type shown in FIGURE 3for profiles taken along the lines AA and BB of FIGURE 2C. It is notedthat the concentration gradient at the source to gate and drain to gateelectrodes is reduced while the concentration gradient between thechannel and gate is maintained relatively high.

A method of producing a transistor structure having relatively lowcapacitance is by out-diffusion from a nearly compensated semiconductiveblock. In general, acceptors diffuse much more rapidly than donors insilicon. Thus, the structure can be made as illustrated in FIGURES 4A-C.A nearly compensated p-type crystal 21 containing to 10 atoms ofarsenic, or antimony three times as much aluminum is out-diffused byheating to a high temperature in the presence of a sink for the impuritysuch as a vacuum of cold trap. Since the aluminum diffuses much morerapidly than the donor, the surface layer 22 will become n-type. Theresulting structure is schematically shown in FIGURE 4A. A groove 23 isthen formed by etching, cutting or the like which extends through then-type layer into the base p-type layer, FIG- URE 4B. A secondout-diffusion is performed for a shorter period of time which results ina thinner n-type layer 24 in the bottom of the groove 23, FIGURE 4C. Thesurface layer on all surfaces except the one containing the source,drain and channel is removed. Suitable contacts are made to the source,drain and gate regions.

The concentration gradients for the structure of FIG- URE along thelines CC and D-D are shown in FIGURE 5. Thus, it is seen that theconcentration gradient at the source to gate, and drain to gatejunctions is considerably reduced while the concentration gradientbetween the channel and the gate remains high.

Referring to FIGURES 6A-C, another method of forming a unipolar fieldeffect transistor which has a low capacity junction with high breakdownvoltage in the gate and drain areas, and an abrupt junction at thechannel is shown. Thus, a block of semiconductive material, for example,weak p-type (p-) has a strong n-type layer (n+) formed thereon. A grooveis then formed which extends through the n+ layer into the player, FIG-URE 6A. A diffusion is then carried out in the presence of acceptors toform a p-type layer (p) in the bottom of the groove. The p-type layershould be weaker than the n+ layer whereby no conversion occurs in theportion 26 of the n-type layer, FIGURE 6B. A subsequent diffusion in thepresence of donor forms an ntype layer (n) in the grooved portion. Thisis then the channel. Source and drain connections are made to therelatively thick n+ edge regions. The resulting structure, FIGURE 6C,has a low capacity junction between source and gate, and drain and gate,and an abrupt junction between the channel and the gate.

Referring to FIGURES 7AB, another method for forming a channel which issmall in two directions is illustrated. A block of n-type material has arelatively thin p-type layer diffused thereon. Two metallic areas 31 arethen formed over the p-type layer by evaporation or plating. The metalcontains an acceptor element such as gold-gallium. The two strips 31 areplaced in close proximity whereby the channel length is of predetermineddesired length. Subsequent to the placing of the metallic areas, themetal is alloyed into the surface. On recrystallization, regions forsource and drain contacts are formed which are either thicker or morehighly doped, or both, than the channel.

An alternative method for producing a structure with lowered capacitanceis illustrated in FIGURE 8. A p+ structure of the type illustrated inFIGURE 8A is made by pulling, rate growing, melt back, orgrown-diffusion technique. A suitable n-type impurity is then diffusedonto this structure. The layers on all sides are removed and the corners32 are cut away. The resulting structure is shown in FIGURE 8B. A thinchannel 33 is formed with relatively thick source and drain regions 34and 36. The charge density along the lines EE and FF are shown in FIGURE9.

Thus, it is seen that a field effect transistor is formed with a channelthat is small in two directions. The source, drain and channel regionsare carried by a massive block of material. The structure providessuitable means for forming relatively thick regions with lowconcentration gradients adjacent the channel to lower the capacitance.Further, means are provided whereby the junction may be tailored toreduce the capacitance and to improve the breakdown characteristics.

We claim:

I. The method of forming a field effect transistor which comprises thesteps of forming a layer of opposite conductivity type on one surface ofa block of semiconductive material of one conductivity type, forming agroove in said layer which extends through the layer into the block, and

diffusing impurity atoms of the type which characterizes said oppositeconductivity from said one surface to form a relatively thin regionforming a junction with the block and connected at its ends with thelayer.

2. The method of forming a field effect transistor which comprises thesteps of forming a block of semiconductive material having impurityatoms characterizing first and second conductivity types insubstantially equal numbers, out-diffusing by heating said block in thepresence of a sink whereby impurities characterizing one conductivitytype diffuse outwardly to form a layer on one surface of the block whichis of different conductivity type than the block to form a rectifyingjunction with the block, forming a groove through said layer extendinginto the block, said subsequently out-diffusing to form a relativelythin region which includes atoms characterizing said one conductivitytype at the bottom of said groove, said region connecting with theadjacent portions of the layer.

3. The method of forming a field effect transistor which comprises thesteps of forming a layer of opposite conductivity type on a block ofsemiconductive material of one conductivity type, forming a groove insaid layer which extends through the layer into the block, diffusingimpurity atoms of said one conductivity type on the surface includingthe layer, the added impurity atoms being less than those required tocompensate said layer of opposite conductivity type, said atoms forminga region of 5 higher impurity concentration in the block at the bottomof the groove, and subsequently diffusing impurity atoms of oppositeconductivity type to form a relatively thin region forming a junctionwith the region of higher impurity concentration in the block andmerging into the layer 10 of opposite conductivity type along the sidesof the groove.

References Cited in the file of this patent UNITED STATES PATENTS PfannNov. 13, 1956 Smith Apr. 16, 1957 Fuller May 27, 1958 Runyan et a1 Mar.17, 1959 Shockley May 10, 1960 Shockley Apr. 18, 1961 FOREIGN PATENTSCanada Dec. 31, 1957

1. THE METHOD OF FORMING A FIELD EFFECT TRANSISTOR WHICH COMPRISES THESTEPS OF FORMING A LAYER OF OPPOSITE CONDUCTIVITY TYPE ON ONE SURFACE OFA BLOCK OF SEMICONDUCTIVE MATERIAL OF ONE CONDUCTIVITY TYPE, FORMING AGROOVE IN SAID LAYER WHICH EXTENDS THROUGH THE LAYER INTO THE BLOCK, ANDDIFFUSING IMPURITY ATOMS OF THE TYPE WHICH CHARACTERIZES SAID OPPOSITECONDUCTIVITY FROM SAID ONE SURFACE TO FORM A RELATIVELY THIN REGIONFORMING A JUNCTION WITH THE BLOCK AND CONNECTED AT ITS ENDS WITH THELAYER.